In recent years, there has been used a three-dimensional mounting technique of stacking and mounting chips within a package, in order to realize the downsizing, thinning, functional upgrading, and performance enhancement of electronic equipment.
Various techniques are available, including a chip layering technique of interconnecting chips by using a through-via (TSV: Through Silicon Via) provided in the LSI chip, a chip layering technique of interconnecting chips within a single package by wire bonding or by using solder bumps, and a package layering technique of stacking a plurality of packages at a package level, in order to three-dimensionally configure an LSI device.
Of the above-described techniques, a technique which holds promise for the highest degree of functional upgrading and performance enhancement is the chip layering technique using TSVs. Unfortunately, however, this technique involves the necessity to form TSVs in a region where any LSI circuits are not present. Thus, the technique is subject to many layout constraints resulting from keep-out zones. In addition, future logic LSIs tend to become smaller in chip size. Accordingly, the technique has difficulty in densifying TSVs. Yet additionally, the technique has the problem that the yield rate of TSV formation affects the yield rate of chips as a whole including a yield in a step of LSI circuit formation, no matter whether the TSV formation is performed before or after the step of LSI circuit formation.
In contrast, the chip layering technique of interconnecting chips within a single package by wire bonding or by using solder bumps can realize three-dimensional configuration with a relatively high yield. Connection terminals on a chip are limited to those on the periphery thereof, however, in the case of interconnection by wire bonding. In addition, it is difficult to stack more than three chips in the case of interconnection using solder bumps. Thus, these chip layering techniques have the problem of difficulty in high-density packaging.
On the other hand, such a package layering technique as package-on-package is widely used with a focus on cellular phone applications for reasons of ease in combining functions and advantage in reducing costs. In package-on-package techniques currently in practical use, however, the pin location of a package to be mounted on an upper stage is limited to a peripheral part. Consequently, a restriction is placed on the number of pins of an LSI chip in a lower-stage package. In addition, package layering techniques have the problem that a height at which packages are mounted is greater, compared with a height in the case of chip layering techniques.
Hence, an LSI-embedded substrate in which an LSI chip is built in a package substrate is a focus of attention as means for realizing thinning, downsizing, and an increase in the number of pins in a package-level three-dimensional structure, particularly in a package-on-package lower-stage structure.
Patent Literature 1 discloses a semiconductor device having a package structure in which a chip is mounted within a wiring board. This semiconductor device includes a core substrate including, on the upper and the lower sides thereof, conductor layers conductive to each other by way of a through-hole; a chip mounted on this core substrate with a circuit-formed surface of the chip facing up; an insulating layer covering this chip; an on-chip wiring line connected to an electrode of this chip; an upper surface-side wiring line of a package connected to this wiring line through a via; and a via for connection with the conductor layers on the core substrate in an insulating layer lateral to the chip. In addition, an insulating layer is provided on the lower surface side of the core substrate, a via conductive to the via lateral to the chip is provided in this insulating layer, and a wiring line for connection with this via is provided on the lower surface side of the package.